據(jù)物理學(xué)家組織網(wǎng)近日?qǐng)?bào)道，美國(guó)科學(xué)家研制出了一種新的集成電路架構(gòu)并做出了模型。在這一架構(gòu)內(nèi)，晶體管和互連設(shè)備無(wú)縫地結(jié)合在一塊石墨烯薄片上。發(fā)表在《應(yīng)用物理快報(bào)》雜志上的這項(xiàng)最新研究將有助于科學(xué)家們制造出能效超高的柔性透明電子設(shè)備。

目前，用來(lái)制造晶體管和互聯(lián)設(shè)備的都是大塊材料，因此很難讓集成電路變得更小，而且大塊材料也容易導(dǎo)致晶體管和互聯(lián)設(shè)備之間的“接觸電阻”變大，而這兩方面都會(huì)降低晶體管和互聯(lián)設(shè)備的性能并增加能耗。基于石墨烯的晶體管和互連設(shè)備極具前景，有望解決這些基本問(wèn)題。

該研究的領(lǐng)導(dǎo)者、加州大學(xué)圣巴巴拉分校（UCSB）電子和計(jì)算機(jī)工程系教授、納米電子設(shè)備研究實(shí)驗(yàn)室主任高斯塔夫·巴納吉表示：“石墨烯除了是目前最纖薄的材料之外，其還具有一個(gè)可調(diào)諧的帶隙。狹窄的石墨烯帶能被用來(lái)制造半導(dǎo)體；而寬的石墨烯帶是金屬。不同的石墨烯帶可以制成不同的設(shè)備，制成的設(shè)備可以無(wú)縫地結(jié)合在一起，這樣也可以降低接觸電阻。”

在實(shí)驗(yàn)中，巴納吉研究團(tuán)隊(duì)使用非平衡格林函數(shù)（NEGF）來(lái)對(duì)包含有如此多異質(zhì)結(jié)構(gòu)的復(fù)雜電路架構(gòu)的性能進(jìn)行評(píng)估，并研究出了一種方法，設(shè)計(jì)出了這種“全石墨烯”的邏輯電路。該研究的合作者康家豪（音譯）表示：“對(duì)電子通過(guò)由不同類型的石墨烯納米帶制造的設(shè)備和互連設(shè)備的情況以及跨過(guò)其接口的情況進(jìn)行精確的評(píng)估是我們的電路設(shè)計(jì)成功并達(dá)到最優(yōu)化的關(guān)鍵。”

石墨烯研究領(lǐng)域的大咖、哥倫比亞大學(xué)的物理學(xué)教授菲利普·吉姆表示：“這項(xiàng)研究通過(guò)使用一種全石墨烯的設(shè)備——互聯(lián)架構(gòu)，為傳統(tǒng)集成電路會(huì)遇到的接觸電阻問(wèn)題提供了一種解決辦法，這將顯著簡(jiǎn)化基于石墨烯的納米電子設(shè)備的集成電路構(gòu)建過(guò)程。”

結(jié)果表明，與目前的集成電路技術(shù)相比，新的全石墨烯電路的噪聲容限更高，且耗費(fèi)的靜態(tài)功耗低很多。另外，巴納吉表示，隨著石墨烯研究領(lǐng)域不斷取得進(jìn)展，這種全石墨烯電路有望在不久的將來(lái)成為現(xiàn)實(shí)。

原文參考：

Researchers Advance Scheme to Design Seamless Integrated Circuits Etched on Graphene

UC Santa Barbara researchers demonstrate seamless designing of an atomically-thin circuit with transistors and interconnects etched on a monolayer of graphene

Researchers in electrical and computer engineering at UC Santa Barbara have introduced and modeled an integrated circuit design scheme in which transistors and interconnects are monolithically patterned seamlessly on a sheet of graphene, a 2-dimensional plane of carbon atoms. The demonstration offers possibilities for ultra energy-efficient, flexible, and transparent electronics.

Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing "contact resistance" between them, both of which lead to degrading performance and rising energy consumption. Graphene-based transistors and interconnects are a promising nanoscale technology that could potentially address issues of traditional silicon-based transistors and metal interconnects.

"In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns - narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices in a seamless fashion and lower interface/contact resistances," explained Kaustav Banerjee, professor of electrical and computer engineering and director of the Nanoelectronics Research Lab at UCSB. Banerjee's research team also includes UCSB researchers Jiahao Kang, Deblina Sarkar and Yasin Khatami. Their work was recently published in the journal Applied Physics Letters.

"Accurate evaluation of electrical transport through the various graphene nanoribbon based devices and interconnects and across their interfaces was key to our successful circuit design and optimization," explained Jiahao Kang, a PhD student in Banerjee's group and a co-author of the study. Banerjee's group pioneered a methodology using the Non-Equilibrium Green's Function (NEGF) technique to evaluate the performance of such complex circuit schemes involving many heterojunctions. This methodology was used in designing an "all-graphene" logic circuit reported in this study.

"This work has demonstrated a solution for the serious contact resistance problem encounterd in conventional semiconductor technology by providing an innovative idea of using an all-graphene device-interconnect scheme. This will significantly simplify the IC fabrication process of graphene based nanoelectronic devices." commented Philip Kim, professor of physics at Columbia University, and a renowned scientist in the graphene world.

As reported in their study, the proposed all-graphene circuits have achieved 1.7X higher noise margins and 1-2 decades lower static power consumption over current CMOS technology. According to Banerjee, with the ongoing worldwide efforts in patterning and doping of graphene, such circuits can be realized in the near future.

"We hope that this work will encourage and inspire other researchers to explore graphene and beyond-graphene emerging 2-dimensional crystals for designing such ‘band-gap engineered' circuits in the near future," added Banerjee.

Their research was supported by the National Science Foundation.