美國加州大學柏克萊分校 （UCBerkeley）的科學家們表示已經(jīng)找到一種可推動芯片電感器 （on-chipinductor）技術進展的新方法，將有助于催生新一代微型射頻 （RF）電子與無線通訊系統(tǒng)設計。

加州大學的研究人員們深入探索在納米磁鐵 （nanomagnet）中納米材料合成的最新發(fā)展。根據(jù)加州大學柏克萊分校機械工程系教授Liwei Lin表示，研究人員們發(fā)現(xiàn)，采用外覆絕緣層的磁性納米粒子可使高頻的芯片電感器尺寸縮小，同時提升性能，同時，通過其高截止頻率提供良好的導磁率，從而降低在高頻作業(yè)時的渦流損耗。

工程師們經(jīng)常面對的問題是，在試圖縮減芯片電感器尺寸的同時，還得保持其最佳電感與性能。Liwei Lin表示這些困難主要來自于“基本科學以及工程實踐約束”所造成的限制。

芯片電感器技術并未發(fā)生像電晶體技術一樣的進展電晶體技術在過去40年來一直遵循摩爾定律。電感器在電路上算是一款被動元件被歸類于“超越摩爾定律”的領域，因此整合的是不會因摩爾定律而微縮的RF與MEMS等非數(shù)位化功能。

芯片電感器架構需要較大的面積，因為在其金屬走線之間需要一定的長度、匝數(shù)、厚度與空間，以實現(xiàn)適當?shù)碾姼信c性能。然而，對于要求較大的面積則可能會因為在旋轉線圈和半導體基板之間產(chǎn)生寄生效應而造成電感損失。

因此，電感器在微型化時必須添加磁性材料，但在這方面也帶來其他的技術限制，例如制程方案、相容于標準制程，以及材料的穩(wěn)定度，Liwei Lin說，磁性材料在磁導率和頻率響應方面存在一些限制。

新的電感器制造技術采用絕緣的納米復合磁性物質作為填充材料來減少芯片電感器尺寸，以及提高達80%的電感，從而使芯片電感器縮減至少50%。此外，LiweiLin強調，它還具有使作業(yè)頻率范圍從GHz級擴展至10GHz的潛力。

他預計電感器技術的這些進展可望在未來3-5年內落實應用于芯片制程中。

原文參考：

UC Berkeley Scientists Advance On-Chip Inductor Technology

by:eetimes

University of California Berkeley scientists say they have found a way to advance on-chip inductor technology, triggering a new generation of miniature RF electronics and wireless communications systems.

The UC research delved into recent developments in nanomaterial synthesis of nanomagnets. Liwei Lin, a professor of mechanical engineering at UC Berkeley, told us the researchers found that using magnetic nanoparticles with a coating of insulators shrinks the size and improves the performance of high-frequency on-chip inductors. "They provide good magnetic permeability with high cutoff frequency while reducing the eddy current losses at high-frequency operations."

Engineers have had problems trying to reduce the size of on-chip inductors while maintaining optimum levels of inductance and performance. Difficulties stem from limitations set by "fundamental sciences and constraints set by engineering practice," Lin said.

On-chip inductor technology hasn't progressed the same way as transistor technology, which has followed Moore's Law over the past 40 years. Inductors -- technically passive elements in circuitry -- fall into the "More Than Moore" domain, in which devices integrate nondigital functions such as RF and MEMS that do not scale to Moore's Law.

When on-chip inductors are constructed, large areas are required, because they need a certain length, number of turns, thickness, and space between metal traces to achieve adequate levels of inductance and performance. However, the large area requirements produce inductance losses because of the parasitic effects between the spiral coil and the semiconductor substrate.

As a result, miniaturization will require the addition of magnetic materials, but they have their own technical limitations, "such as processing schemes, compatibility with standard processes, and material stabilities," Lin said. "Magnetic materials have fundamental limits on their permeability and frequency responses."

The new inductor fabrication technology, which uses insulated nano-composite magnetic materials as the filling material to reduce the size of the on-chip inductors, enhances inductance by up to 80%, resulting in at least 50% shrinkage in the on-chip inductor. It also has the potential to extend the operational frequency range from the GHz range to the 10-GHz range, Lin said.

He expects these advancements to be applied to the chip manufacturing process in 3-5 years.

The UC Berkeley research has been sponsored by Semiconductor Research Corp., the university research consortium for semiconductors and related technologies in Research Triangle Park, N.C.