ADI 公司的ADRF6655是集成了PLL和VCO的高動(dòng)態(tài)范圍的有源混頻器, 輸入頻率范圍100MHz - 2500 MHz,內(nèi)部LO頻率范圍從1050 MHz 到2300 MHz,輸入P1dB為12dBm,輸入IP3為29dBm,噪音(SSB)為12dB,電壓轉(zhuǎn)換增益6dB,200歐姆輸出匹配阻抗. ADRF6655主要用在寬帶通信設(shè)備如點(diǎn)對(duì)點(diǎn)微波通信,無線基站,國(guó)防寬帶和軟件定義無線電(SDR),蜂窩中繼器以及通信測(cè)試設(shè)備.本文介紹ADRF6655主要特性, 功能方框圖, PLL和VCO方框圖,以及850MHz, 900MHz, 1200MHz, 1300MHz, 1600MHz和2100MHz輸出匹配網(wǎng)絡(luò),評(píng)估板電路圖和評(píng)估板配置元件表.
The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is then applied to a local oscillator (LO) divider as well as to a programmable PLL divider. The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047.
The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a −40℃ to +85℃ temperature range.
ADRF6655主要特性:
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
圖1. ADRF6655功能方框圖
圖2. ADRF6655 PLL和VCO方框圖
圖3. ADRF6655混頻器方框圖
圖4. ADRF6655 850MHz輸出匹配網(wǎng)絡(luò)圖(800MHz-925MHz輸出回波損耗大于12dB)
圖5. ADRF6655 900MHz輸出匹配網(wǎng)絡(luò)圖(815MHz-1075MHz輸出回波損耗大于12dB)
圖6. ADRF6655 1200MHz輸出匹配網(wǎng)絡(luò)圖(950MHz-1500MHz輸出回波損耗大于12dB)
圖7. ADRF6655 1300MHz輸出匹配網(wǎng)絡(luò)圖(1075MHz-1525MHz輸出回波損耗大于12dB)
圖8. ADRF6655 1600MHz輸出匹配網(wǎng)絡(luò)圖(140MHz-1680MHz輸出回波損耗大于12dB)
圖9. ADRF6655 2100MHz輸出匹配網(wǎng)絡(luò)圖(2000MHz-2200MHz輸出回波損耗大于12dB)
圖10. ADRF6655評(píng)估板電路圖
ADRF6655評(píng)估板配置元件表:
詳情請(qǐng)見:
http://www.analog.com/static/imported-files/data_sheets/ADRF6655.pdf
The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is then applied to a local oscillator (LO) divider as well as to a programmable PLL divider. The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047.
The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a −40℃ to +85℃ temperature range.
ADRF6655主要特性:
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
圖1. ADRF6655功能方框圖
圖2. ADRF6655 PLL和VCO方框圖
圖3. ADRF6655混頻器方框圖
圖4. ADRF6655 850MHz輸出匹配網(wǎng)絡(luò)圖(800MHz-925MHz輸出回波損耗大于12dB)
圖5. ADRF6655 900MHz輸出匹配網(wǎng)絡(luò)圖(815MHz-1075MHz輸出回波損耗大于12dB)
圖6. ADRF6655 1200MHz輸出匹配網(wǎng)絡(luò)圖(950MHz-1500MHz輸出回波損耗大于12dB)
圖7. ADRF6655 1300MHz輸出匹配網(wǎng)絡(luò)圖(1075MHz-1525MHz輸出回波損耗大于12dB)
圖8. ADRF6655 1600MHz輸出匹配網(wǎng)絡(luò)圖(140MHz-1680MHz輸出回波損耗大于12dB)
圖9. ADRF6655 2100MHz輸出匹配網(wǎng)絡(luò)圖(2000MHz-2200MHz輸出回波損耗大于12dB)
圖10. ADRF6655評(píng)估板電路圖
ADRF6655評(píng)估板配置元件表:
詳情請(qǐng)見:
http://www.analog.com/static/imported-files/data_sheets/ADRF6655.pdf
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